Challenges and Emerging Solutions in Testing TSV-Based 21⁄2 D-and 3D-Stacked ICs
نویسنده
چکیده
Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5Dand 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5Dand 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.
منابع مشابه
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
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